industrial temperature range idt74alvch162268 3.3v cmos 12-bit to 24-bit registered bus exchanger 1 january 2004 industrial temperature range the idt logo is a registered trademark of integrated device technology, inc. ? 2004 integrated device technology, inc. dsc-4535/2 features: ? 0.5 micron cmos technology ? typical t sk(o) (output skew) < 250ps ? esd > 2000v per mil-std-883, method 3015; > 200v using machine model (c = 200pf, r = 0) ?v cc = 3.3v 0.3v, normal range ?v cc = 2.7v to 3.6v, extended range ?v cc = 2.5v 0.2v ? cmos power levels (0.4 w typ. static) ? rail-to-rail output swing for increased noise margin ? available in tssop and tvsop packages functional block diagram description: this 12-bit to 24-bit registered bus exchanger is built using advanced dual metal cmos technology. this device is used for applications in which data must be transferred from a narrow high-speed bus to a wide, lower- frequency bus. the alvch162268 device provides synchronous data exchange be- tween the two ports. data is stored in the internal registers on the low-to- high transition of the clock (clk) input when the appropriate clock-enable ( clken ) inputs are low. the select ( sel ) line is synchronous with clk and selects 1b or 2b input data for the a outputs. for data transfer in the a-to- b direction, a two-stage pipeline is provided in the a-to-1b path, with a single storage register in the a-to-2b path. proper control of these inputs allows two sequential 12-bit words to be presented as a 24-bit word on the b-port. data flow is controlled by the active-low output enables ( oea and oeb ). these control terminals are registered to synchronize the bus-direction changes with clk. the alvch162268 has series resistors in the device output structure of the ?b? port which will significantly reduce line noise when used with light loads. this driver has been designed to drive 12ma at the designated threshold levels. the ?a? port has a 24ma driver. the alvch162268 has ?bus-hold? which retains the inputs? last state whenever the input bus goes to a high impedance. this prevents floating inputs and eliminates the need for pull-up/down resistors. applications: ? 3.3v high speed systems ? 3.3v and lower voltage computing systems drive features: ? high output drivers: 24ma (a port) ? balanced output drivers: 12ma (b port) idt74alvch162268 3.3v cmos 12-bit to 24-bit registered bus ex- changer with 3-state outputs and bus-hold clken2b clk clkena1 oea 1 b 1 sel clkena2 c1 1d c1 1d ce 1d c1 a 1 2 b 1 1 of 12 channels clken1b 1 28 56 55 30 27 2 29 oeb ce 1d c1 ce 1d c1 ce 1d c1 ce 1d c1 23 6 8 c1 1d 0 1
industrial temperature range 2 idt74alvch162268 3.3v cmos 12-bit to 24-bit registered bus exchanger tssop/ tvsop top view pin configuration oea 2 b 3 gnd 2 b 2 2 b 1 v cc a 1 a 2 gnd a 3 a 4 a 5 a 6 a 8 a 9 gnd a 10 a 11 a 12 v cc 1 b 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 48 49 50 51 52 53 54 55 56 1 oeb 2 b 4 gnd 2 b 5 2 b 6 v cc 2 b 7 2 b 8 2 b 9 2 b 10 2 b 11 2 b 12 gnd 1 b 11 1 b 10 1 b 9 1 b 8 gnd 1 b 7 1 b 6 1 b 5 gnd 1 b 3 sel 25 26 27 28 32 31 30 29 gnd 1 b 4 clkena1 clk a 7 1 b 2 v cc 1 b 12 clkena2 clken2b clken1b note: 1. as applicable to the device type. symbol parameter (1) conditions typ. max. unit c in input capacitance v in = 0v 5 7 pf c out output capacitance v out = 0v 7 9 pf c i/o i/o port capacitance v in = 0v 7 9 pf symbol description max unit v term (2) terminal voltage with respect to gnd ?0.5 to +4.6 v v term (3) terminal voltage with respect to gnd ?0.5 to v cc +0.5 v t stg storage temperature ?65 to +150 c i out dc output current ?50 to +50 ma i ik continuous clamp current, 50 ma v i < 0 or v i > v cc i ok continuous clamp current, v o < 0 ?50 ma i cc continuous current through each 100 ma i ss v cc or gnd absolute maximum ratings (1) notes: 1. stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. v cc terminals. 3. all terminals except v cc . capacitance (t a = +25c, f = 1.0mhz) function tables (1) inputs outputs clkena1 clkena2 clk ax 1bx 2bx hhxx1b 0 (2) 2b 0 (2) ll ll (3) l ll hh (3) h xl lxl xl hxh inputs outputs clk oea oeb ax 1bx, 2bx hh z z h l z active l h active z l l active active output enable a-to-b storage ( oeb = l and oea = h)
industrial temperature range idt74alvch162268 3.3v cmos 12-bit to 24-bit registered bus exchanger 3 note: 1. h = high voltage level l = low voltage level x = don?t care z = high impedance = low-to-high transition 2. output level before the indicated steady-state input conditions were established. 3. two clk edges are needed to propagate data. pin names i/o description ax (1:12) i/o bidirectional data port a. usually connected to the cpu's address/data bus. (1) 1bx (1:12) i/o bidirectional data port 1b. usually connected to the even path or even bank of memory. (1) 2bx (1:12) i/o bidirectional data port 2b. usually connected to the odd path or odd bank of memory. (1) clk i clock input clkena1 i clock enable input for the a-1b register. if clkena1 is low during the rising edge of clk, data will be clocked into register a-1b (active low). clkena2 i clock enable input for the a-1b register. if clkena2 is low during the rising edge of clk, data will be clocked into register a-2b (active low). clken1b i clock enable input for the a-1b register. if clken1b is low during the rising edge of clk, data will be clocked into register 1b-a (active low). clken2b i clock enable input for the a-1b register. if clken2b is low during the rising edge of clk, data will be clocked into register 2b-a (active low). sel i 1b or 2b port selection. when high during the rising edge of clk, sel enables data transfer from 1b port to a port. when low during the rising edge of clk, sel enables data transfer from 2b port to a port (active low). oea i synchronous output enable for a port (active low) oeb i synchronous output enable for a port (active low) pin description inputs output clken1b clken2b clk sel 1bx 2bx ax hxxhxxa 0 (2) xhxlxxa 0 (2) lx hlxl lx hhxh xl lxll xl lxhh b-to-a storage ( oea = l and oea = h) function tables (continued) (1) note: 1. these pins have "bus-hold". all other pins are standard inputs, outputs, or i/os.
industrial temperature range 4 idt74alvch162268 3.3v cmos 12-bit to 24-bit registered bus exchanger symbol parameter test conditions min. typ. (1) max. unit v ih input high voltage level v cc = 2.3v to 2.7v 1.7 ? ? v v cc = 2.7v to 3.6v 2 ? ? v il input low voltage level v cc = 2.3v to 2.7v ? ? 0.7 v v cc = 2.7v to 3.6v ? ? 0.8 i ih input high current v cc = 3.6v v i = v cc ?? 5a i il input low current v cc = 3.6v v i = gnd ? ? 5a i ozh high impedance output current v cc = 3.6v v o = v cc ?? 10 a i ozl (3-state output pins) v o = gnd ? ? 10 v ik clamp diode voltage v cc = 2.3v, i in = ?18ma ? ?0.7 ?1.2 v v h input hysteresis v cc = 3.3v ? 100 ? mv i ccl quiescent power supply current v cc = 3.6v ? 0.1 40 a i cch v in = gnd or v cc i ccz ? i cc quiescent power supply current one input at v cc - 0.6v, other inputs at v cc or gnd ? ? 750 a variation dc electrical characteristics over operating range following conditions apply unless otherwise specified: operating condition: t a = ?40c to +85c note: 1. typical values are at v cc = 3.3v, +25c ambient. bus-hold characteristics symbol parameter (1) test conditions min. typ. (2) max. unit i bhh bus-hold input sustain current v cc = 3v v i = 2v ? 75 ? ? a i bhl v i = 0.8v 75 ? ? i bhh bus-hold input sustain current v cc = 2.3v v i = 1.7v ? 45 ? ? a i bhl v i = 0.7v 45 ? ? i bhho bus-hold input overdrive current v cc = 3.6v v i = 0 to 3.6v ? ? 500 a i bhlo notes: 1. pins with bus-hold are identified in the pin description. 2. typical values are at v cc = 3.3v, +25c ambient.
industrial temperature range idt74alvch162268 3.3v cmos 12-bit to 24-bit registered bus exchanger 5 note: 1. v ih and v il must be within the min. or max. range shown in the dc electrical characteristics over operating range table for the appropriat e v cc range. t a = ? 40c to + 85c. output drive characteristics (b port) symbol parameter test conditions (1) min. max. unit v oh output high voltage v cc = 2.3v to 3.6v i oh = ? 0.1ma v cc ? 0.2 ? v v cc = 2.3v i oh = ? 4ma 1.9 ? i oh = ? 6ma 1.7 ? v cc = 2.7v i oh = ? 4ma 2.2 ? i oh = ? 8ma 2 ? v cc = 3v i oh = ? 6ma 2.4 ? i oh = ? 12ma 2 ? v ol output low voltage v cc = 2.3v to 3.6v i ol = 0.1ma ? 0.2 v v cc = 2.3v i ol = 4ma ? 0.4 i ol = 6ma ? 0.55 v cc = 2.7v i ol = 4ma ? 0.4 i ol = 8ma ? 0.6 v cc = 3v i ol = 6ma ? 0.55 i ol = 12ma ? 0.8 note: 1. v ih and v il must be within the min. or max. range shown in the dc electrical characteristics over operating range table for the appropriat e v cc range. t a = ? 40c to + 85c. output drive characteristics (a port) symbol parameter test conditions (1) min. max. unit v oh output high voltage v cc = 2.3v to 3.6v i oh = ? 0.1ma v cc ? 0.2 ? v v cc = 2.3v i oh = ? 6ma 2 ? v cc = 2.3v i oh = ? 12ma 1.7 ? v cc = 2.7v 2.2 ? v cc = 3v 2.4 ? v cc = 3v i oh = ? 24ma 2 ? v ol output low voltage v cc = 2.3v to 3.6v i ol = 0.1ma ? 0.2 v v cc = 2.3v i ol = 6ma ? 0.4 i ol = 12ma ? 0.7 v cc = 2.7v i ol = 12ma ? 0.4 v cc = 3v i ol = 24ma ? 0.55 operating characteristics, t a = 25c v cc = 2.5v 0.2v v cc = 3.3v 0.3v symbol parameter test conditions typical typical unit c pd power dissipation capacitance outputs enabled c l = 0pf, f = 10mhz 87 120 pf c pd power dissipation capacitance outputs disabled 80 118
industrial temperature range 6 idt74alvch162268 3.3v cmos 12-bit to 24-bit registered bus exchanger switching characteristics (a port) (1) v cc = 2.5v 0.2v v cc = 2.7v v cc = 3.3v 0.3v symbol parameter min. max. min. max. min. max. unit f max 120 ? 125 ? 150 ? mhz t plh propagation delay 1.6 5.8 ? 5.4 1.7 4.8 ns t phl clk to ax (1b) t plh propagation delay 1.6 5.8 ? 5.3 1.8 4.8 ns t phl clk to ax (2b) t plh propagation delay 2.5 7.3 ? 6.5 2.4 5.8 ns t phl clk to ax ( sel ) t pzh output enable time 2 6.2 ? 5.6 1.8 5.1 ns t pzl clk to ax t phz output disable time 2 6.5 ? 5.4 2.1 5 ns t plz clk to ax t su set-up time, ax data before clk 4.5 ? 4 ? 3.4 ? ns t su set-up time, sel before clk 1.4 ? 1.6 ? 1.3 ? ns t su set-up time, clkena1 or clkena2 before clk 3.6 ? 3.4 ? 2.8 ? ns t su set-up time, oea before clk 4.2 ? 3.9 ? 3.2 ? ns t h hold time, ax data after clk 0 ? 0 ? 0.2 ? ns t h hold time, sel after clk 1 ? 1 ? 1 ? ns t h hold time, clkena1 or clkena2 after clk 0.1 ? 0.1 ? 0.4 ? ns t h hold time, oea after clk 0 ? 0 ? 0.2 ? ns t w pulse width, clk high or low 3.3 ? 3.3 ? 3.3 ? ns t sk(o) output skew (2) ????? 500 ps notes: 1. see test circuits and waveforms. t a = ? 40c to + 85c. 2. skew between any two outputs of the same package and switching in the same direction. switching characteristics (b port) (1) v cc = 2.5v 0.2v v cc = 2.7v v cc = 3.3v 0.3v symbol parameter min. max. min. max. min. max. unit f max 120 ? 125 ? 150 ? mhz t plh propagation delay 1.6 6.1 ? 5.9 1.8 5.4 ns t phl clk to 1bx or 2bx t pzh output enable time 2.7 7.2 ? 6.8 2.6 6.1 ns t pzl clk to 1bx or 2bx t phz output disable time 2.8 7.2 ? 6.1 2.5 5.9 ns t plz clk to 1bx or 2bx t su set-up time, bx data before clk 0.8 ? 1.2 ? 1 ? ns t su set-up time, clken1b or clken2b before clk 3.2 ? 3 ? 2.5 ? ns t su set-up time, oeb before clk 4.2 ? 3.9 ? 3.2 ? ns t h hold time, bx data after clk 1.3 ? 1.2 ? 1.3 ? ns t h hold time, clken1b or clken2b after clk 0.1 ? 0 ? 0.5 ? ns t h hold time, oeb after clk 0 ? 0 ? 0.2 ? ns t sk(o) output skew (2) ????? 500 ps notes: 1. see test circuits and waveforms. t a = ? 40c to + 85c. 2. skew between any two outputs of the same package and switching in the same direction.
industrial temperature range idt74alvch162268 3.3v cmos 12-bit to 24-bit registered bus exchanger 7 open v load gnd v cc pulse generator d.u.t. 500 ? 500 ? c l r t v in v out (1, 2) alvc link input v ih 0v v oh v ol t plh1 t sk (x) output 1 output 2 t phl1 t sk (x) t plh2 t phl2 v t v t v oh v t v ol t sk (x) = t plh2 - t plh1 or t phl2 - t phl1 alvc link same phase input transition opposite phase input transition 0v 0v v oh v ol t plh t phl t phl t plh output v ih v t v t v ih v t alvc link data input 0v 0v 0v 0v t rem timing input synchronous control t su t h t su t h v ih v t v ih v t v ih v t v ih v t alvc link asynchronous control low-high-low pulse high-low-high pulse v t t w v t alvc link control input t plz 0v output normally low t pzh 0v switch closed output normally high enable disable switch open t phz 0v v lz v oh v t v t t pzl v load/2 v load/2 v ih v t v ol v hz alvc link test circuits and waveforms propagation delay test circuit for all outputs enable and disable times set-up, hold, and release times notes: 1. for t sk (o) output1 and output2 are any two outputs. 2. for t sk (b) output1 and output2 are in the same bank. definitions: c l = load capacitance: includes jig and probe capacitance. r t = termination resistance: should be equal to z out of the pulse generator. notes: 1. pulse generator for all pulses: rate 1.0mhz; t f 2.5ns; t r 2.5ns. 2. pulse generator for all pulses: rate 1.0mhz; t f 2ns; t r 2ns. output skew - t sk ( x ) pulse width note: 1. diagram shown for input control enable-low and input control disable-high. symbol v cc (1) = 3.3v0.3v v cc (1) = 2.7v v cc (2) = 2.5v0.2v unit v load 6 6 2 x vcc v v ih 2.7 2.7 vcc v v t 1.5 1.5 vcc / 2 v v lz 300 300 150 mv v hz 300 300 150 mv c l 50 50 30 pf test conditions switch position test switch open drain disable low v load enable low disable high gnd enable high all other tests open
industrial temperature range 8 idt74alvch162268 3.3v cmos 12-bit to 24-bit registered bus exchanger ordering information idt xx alvc xxx xx package device type temp. range pa pf 162 74 thin shrink small outline package thin very small outline package 12-bit to 24-bit registered bus exchanger with 3-state outputs ?40c to +85c xxx family bus-hold 268 bus-hold double-density with resistors, 24ma (a port) 12ma (b port) h corporate headquarters for sales: for tech support: 2975 stender way 800-345-7015 or 408-727-6116 logichelp@idt.com santa clara, ca 95054 fax: 408-492-8674 (408) 654-6459 www.idt.com
|
